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1 ? fn8158.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyri ght intersil americas inc. 2005, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. x9110 dual supply/low powe r/1024-tap/spi bus single digitally-controlled (xdcp?) potentiometer the x9110 integrates a single digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 1023 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and four non-volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. power-up recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? 1024 resistor taps ? 10-bit resolution ? spi serial interface for write, read, and transfer operations of the potentiometer ? wiper resistance, 40 typical @ 5v ? four non-volatile data registers ? non-volatile storage of multiple wiper positions ? power-on recall. loads saved wiper position on power-up ? standby current < 3a max ? system v cc : 2.7v to 5.5v operation ? analog v+/v-: -5v to +5v ?100k end to end resistance ? 100 yr. data retention ? endurance: 100, 000 data changes per bit per register ? 14 ld tssop ? dual supply version of the x9111 ? low power cmos ? pb-free available (rohs compliant) pinout x9110 14 ld tssop top view functional diagram v cc r l v ss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 a0 r w sck cs r h s0 v+ si hold wp v- r h r l bus r w interface & control pot v cc v ss spi bus address data status write read wiper 1024-taps transfer nc nc 100k power-on recall wiper counter register (wcr) data registers (dr0-dr3) control interface v+ v- data sheet february 13, 2008
2 fn8158.3 february 13, 2008 detailed functional diagram ordering information part number part marking vcc limits (v) potentiomete r range (k ) temp range (c) package pkg. dwg. # x9110tv14 x9110tv 5 10 100 0 to +70 14 ld tssop m14.173 x9110tv14z* (note) x9110tv z 0 to +70 14 ld tssop (pb-free) m14.173 x9110tv14i x9110tv i -40 to +85 14 ld tssop m14.173 x9110tv14iz (note) x9110tv z i -40 to +85 14 ld tssop (pb-free) m14.173 x9110tv14-2.7 x9110tv f 2.7 to 5.5 0 to +70 14 ld tssop m14.173 x9110tv14z-2.7 (note) x9110tv z f 0 to +70 14 ld tssop (pb-free) m14.173 x9110tv14i-2.7 x9110tv g -40 to +85 14 ld tssop m14.173 x9110tv14iz-2.7* (note) x9110tv z g -40 to +85 14 ld tssop (pb-free) m14.173 *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materi als and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free solderin g operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. cs sck a0 so si hold wp interface and control circuitry v- v+ v cc v ss dr0 dr1 dr2 dr3 wiper counter register (wcr) r h r l data r w 1024-taps 100k control power on recall x9110
3 fn8158.3 february 13, 2008 circuit level applications ? vary the gain of a voltage amplifier ? provide programmable dc reference voltages for comparators and detectors ? control the volume in audio circuits ? trim out the offset voltage error in a voltage amplifier circuit ? set the output voltag e of a voltage regulator ? trim the resistance in wheatstone bridge circuits ? control the gain, characteristic frequency and q-factor in filter circuits ? set the scale factor and zero point in sensor signal conditioning circuits ? vary the frequency and duty cycle of timer ics ? vary the dc biasing of a pin diode attenuator in rf circuits ? provide a control variable (i, v, or r) in feedback circuits system level applications ? adjust the contrast in lcd displays ? control the power level of led transmitters in communication systems ? set and regulate the dc biasing point in an rf power amplifier in wireless systems ? control the gain in audio and home entertainment systems ? provide the variable dc bias for tuners in rf wireless systems ? set the operating points in temperature control systems ? control the operating point for sensors in industrial systems ? trim offset and gain errors in artificial intelligent systems bus interface pins serial output (so) so is a serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out on the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses and data to be written to the po ts and pot registers are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9110. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a0) the address input is used to set the 8-bit slave address. a match in the slave address serial data stream a0 must be made with the address input (a0) in order to initiate communication with the x9110. chip select (cs ) when cs is high, the x9110 is deselected and the so pin is at high impedance, and (unles s an internal write cycle is underway) the device will be in the standby state. cs low enables the x9110, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. pin descriptions pin (tssop) symbol function 1 v+ analog supply voltage 2 so serial data output 3 a0 device address 4 sck serial clock 5wp hardware write protect 6 si serial data input 7v ss system ground 8v - analog supply voltage 9cs chip select 10 hold device select. pause the serial bus 11 r w wiper terminal of the potentiometer 12 r h high terminal of the potentiometer 13 r l low terminal of the potentiometer 14 v cc system supply voltage pin descriptions (continued) pin (tssop) symbol function x9110
4 fn8158.3 february 13, 2008 potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. bias supply pins system supply voltage (v cc ) and supply ground (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. analog supply voltages (v+ and v - ) these supplies are the analog voltage supplies for the potentiometer. the v+ supply is tied to the wiper switches while the v- supply is used to bias the switches and the internal p+ substrate of the inte grated circuit. both of these supplies set the voltage limits of the potentiometer. principles of operation device description serial interface the x9110 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked-in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. array description the x9110 is comprised of a resistor array (figure 1). the array contains the equivalent of 1023 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within the individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the 10-bits of the wcr (wcr[9:0]) are decoded to select, and enable, one of 1024 switches. wiper counter register (wcr) the x9110 contains a wiper counter register (see table 1) for the xdcp potentiometer. the wcr is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. the contents of the wcr can be altered in one of three ways: (1) it may be writte n directly by the host via the write wiper counter register instruction (serial load); (2) it serial data path from interface register 0 serial bus input parallel bus input counter register r h r l r w 10 10 c o u n t e r d e c o d e if wcr = 000[hex] then r w = r l if wcr = 3ff[hex] then r w = r h wiper (wcr) (dr0) circuitry register 1 (dr1) register 2 (dr2) register 3 (dr3) figure 1. detailed potentiometer block diagram x9110
5 fn8158.3 february 13, 2008 may be written indirectly by tr ansferring the contents of one of four associated data registers via the xfr data register; (3) it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x911 0 is powered-down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. power-up guidelines are recommended to ensure proper loadings of the dr0 value into the wcr. data registers (dr) the potentiometer has four 10-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the wiper counter register. all operations changing data in one of the da ta registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not r equire storage of multiple settings for the potentiometer, the data registers can be used as regular memory locati ons for system parameters or user preference data. dr[9:0] is used to store one of the 1024 wiper position (0~1023) (see table 2). status register (sr) this 1-bit status register is used to store the system status (see table 3). wip: write in progress st atus bit, read only. ? when wip = 1, indicates that high-voltage write cycle is in progress. ? when wip=0, indicates that no high-voltage write cycle is in progress. table 3. status register, sr (1-bit) table 1. wiper control register, wcr (10-bit), wcr9?wcr0: used to store the current wiper position (volatile, v) wcr9 wcr8 wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvvvv (msb) (lsb) table 2. data register, dr (10-bit), bit 9?bit 0: used to store wiper positions or data (non-volatile, nv) bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nv nv nv nv nv nv nv nv nv nv msb lsb wip (lsb) x9110
6 fn8158.3 february 13, 2008 table 4. identification byte format table 5. instruction byte format device instructions identification byte (id and a) the first byte sent to the x9110 from the host, following a cs going high to low, is called the identification byte. the most significant four bits of the slave address are a device type identifier. the id[3:0] bits is the device id for the x9110; this is fixed as 0101[b] (refer to table 4). the a0 bit in the id byte is the internal slave address. the physical device address is defined by the state of the a0 input pin. the slave address is externa lly specified by the user. the x9110 compares the serial data stream with the address input state; a successful compare of the address bit is required for the x9110 to successfully continue the command sequence. only the device whose slave address matches the incoming device address sent by the master executes the instruction. the a0 input can be actively dr iven by cmos input signals or tied to v cc or v ss . the r/w bit is used to set the device to either read or write mode. instruction byte and register selection the next byte sent to the x911 0 contains the instruction and register pointer information. th e three most significant bits are used provide the instruction opcode (i[2:0]). the rb and ra bits point to one of the four registers. the format is shown in table 5. five of the seven instructions are four bytes in length. these instructions are: ? read wiper counter register ? read the current wiper position of the selected pot ? write wiper counter register ? change current wiper position of the selected pot ? read data register ? read the contents of the selected data register ? write data register ? write a new value to the selected data register ? read status ? this command returns the contents of the wip bit which indicates if the internal write cycle is in progress the basic sequence of the four by te instructions is illustrated in figure 3. these four-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between the potentiometer and one of its associated registers. the read status register instruction is the only unique format (see figure 4). two instructions require a two-byte sequence to complete (see figure 2). these instructions transfer data between the host and the x9110; either bet ween the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: ? xfr data register to wiper counter register ? this transfers the contents of one specified data register to the associated wiper counter register ? xfr wiper counter register to data register ? this transfers the contents of the specified wiper counter register to the specified associated data register see instruction format for more details. id3 id2 id1 id0 0 0 a0 r/w 0101 (msb) (lsb) device type identifier internal slave address read or write bit i2 i1 i0 0 rb ra 0 0 (msb) (lsb) instruction opcode register selection rb ra register 0 0 1 1 0 1 0 1 dr0 dr1 dr2 dr3 x9110
7 fn8158.3 february 13, 2008 write in process (wip bit) the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command (see figure 4). power-up and down requirements at all times, the v+ voltage mu st be greater than or equal to the voltage at r h or r l , and the voltage at r h or r l must be greater than or equal to the voltage at v-. during power-up and power-down, v cc , v+, and v- must reach their final values within 1msec of each other. id3 id2 id1 id0 0 0 a0 i2 i1 i0 rb ra sck si cs 0101 r/w device id internal instruction opcode address register 0 0 0 0 address 0 0 0 figure 2. two-byte instruction sequence id3 id2 id1 id0 0 a0 r/w i2 00 sck si 0 0 x x0 0 xx x w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs i1 i0 0 rb ra 0 101 0 xx x device id internal address instruction opcode register address wiper position 0 figure 3. four-byte instruction sequence (w rite or read for wcr or data registers) id3 id2 id1 id0 0 a0 r/w i2 00 sck si 1 0 x x0 0 xxx wip cs i1 i0 0 rb ra 0101 0 xx x device id internal address instruction opcode register address status bit x x 0 00 0 0 0 0 0 0 figure 4. four-byte instruction sequence (read status registers) x9110
8 fn8158.3 february 13, 2008 instruction format table 6. instruction set instruction instruction set operation r/w i 2 i 1 i 0 0rbra0 0 read wiper counter register 1 1 0 0 0 0 0 0 0 read the contents of the wiper counter register write wiper counter register 0 1 0 1 0 0 0 0 0 write new value to the wiper counter register read data register 1 1 0 1 0 1/0 1/0 0 0 read the contents of the data register pointed to rb-ra write data register 0 1 1 0 0 1/0 1/0 0 0 write new value to the data register pointed to rb-ra xfr data register to wiper counter register 1 1 1 0 0 1/0 1/0 0 0 transfer the contents of the data register pointed to by rb-ra to the wiper counter register xfr wiper counter register to data register 0 1 1 1 0 1/0 1/0 0 0 transfer the contents of the wiper counter register to the data register pointed to by rb-ra read status (wip bit) 1 0 1 0 0 0 0 0 1 read the status of the internal write cycle, by checking the wip bit (read status register). note: 1/0 = data is one or zero read wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode register addresses wiper position (sent by x9110 on so) wiper position (sent by x9110 on so) cs rising edge 010100a0 r/ w = 1 10000000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 write wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode register addresses wiper position (sent by master on si) wiper position (sent by master on si) cs rising edge 010100a0 r/ w = 0 10100000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 read data register (dr) cs falling edge device type identifier device addresses instruction opcode register addresses wiper position (sent by x9110 on so) wiper position (sent by x9110 on so) cs rising edge 010100a0 r/ w = 1 1010rbra00 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 x9110
9 fn8158.3 february 13, 2008 notes: 1. ?a0?: stands for the device address sent by the master. 2. wcrx refers to wiper position data in the wiper counter register 3. ?x?: don?t care. write data register (dr) cs falling edge device type identifier device addresses instruction opcode register address wiper position or data (sent by master on si) wiper position or data (sent by master on si) cs rising edge high-voltage write cycle 010100a0 r/ w = 0 1100rbra0 0xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 transfer data register (dr) to wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode register address cs rising edge 010100a0 r/ w = 1 1100rbra00 transfer wiper counter register (wcr) to data register (dr) cs falling edge device type identifier device addresses instruction opcode register address cs rising edge high-voltage write cycle 010100a0 r/ w = 0 1 1 1 0 rb ra 0 0 read status register (sr) cs falling edge device type identifier device addresses instruction opcode register addresses status data (sent by slave on so) status data (sent by slave on so) cs rising edge 010100a0 r/ w = 1 010x0001xxxxxxxx0000000wip x9110
10 fn8158.3 february 13, 2008 absolute maximum rati ngs thermal information voltage on sck any address input with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v voltage on v+ (referenced to v ss ) (note 8) . . . . . . . . . . . . . . . .10v voltage on v- (referenced to v ss ) (note 8) . . . . . . . . . . . . . . . . -10v (v+) - (v-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v any voltage on r h /r l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v+ any voltage on r l /r h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma thermal resistance (typical, note 4) ja (c/w) 14 lead tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 temperature under bias . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage (v cc ) limits (note 8) x9110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% x9110-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. analog specifications over recommended industrial (2.7v) operation conditions unless otherwise stated. symbol parameter test conditions min (note 13) typ max (note 13) units r total end to end resistance 100 k end to end resistance tolerance 20 % power rating +25c, each potentiometer 50 mw i w wiper current 3 ma r w wiper resistance wiper current = 3ma, v cc = 3v 150 500 r w wiper resistance i w = 3ma, v cc = 5v 100 vv+ voltage on v+ pin x9110 (note 8) +4.5 +5.5 v x9110-2.7 (note 8) +2.7 +5.5 v vv- voltage on v- pin x9110 (note 8) -5.5 -4.5 v x9110-2.7 (note 8) -5.5 -2.7 v v term voltage on any r h or r l pin v ss = 0v v- v+ v noise ref: 1v -120 dbv resolution 0.1 % absolute linearity (note 5) r w(n)(actual) ? r w(n)(expected) , where n = 8 to 1006 1 mi (note 7) r w(n)(actual) ? r w(n)(expected) (note 9) 1.5 mi (note 7) relative linearity (note 6) r w(m + 1) ? [r w(m) + mi], where m = 8 to 1006 0.5 mi (note 7) r w(m + 1) ? [r w(m) + mi] (note 9) 1 mi (note 7) temperature coefficient of r total 300 ppm/c ratiometric temp. coefficient 20 ppm/c c h /c l /c w potentiometer capacitancies see macro model 10/10/25 pf notes: 5. absolute linearity is utilized to determi ne actual wiper voltage versus expected vo ltage as determined by wiper position when used as a potentiometer. 6. relative linearity is utilized to determine the actual change in voltage between two successive tap positi ons when used as a potentiometer. it is a measure of the error in step size. 7. mi = rtot/1023 or (r h ? r l )/1023, single pot 8. v cc , v+, v- must reach their final va lues within 1ms of each other. 9. n = 0, 1, 2, ?,1023; m = 0, 1, 2, ?, 1022. x9110
11 fn8158.3 february 13, 2008 d.c. operating specifications over the recommended operating conditions unless otherwise specified . symbol parameter test conditions min (note 13) typ max (note 13) units i cc1 v cc supply current (active) f sck = 2.5 mhz, so = open, v cc = 5.5v other inputs = v ss 400 a i cc2 v cc supply current (nonvolatile write) f sck = 2.5mhz, so = open, v cc = 5.5v other inputs = v ss 15ma i sb v cc current (standby) sck = si = v ss , addr. = v ss , cs = v cc = 5.5v 3a i li input leakage current v in = v ss to v cc 10 a i lo output leakage current v out = v ss to v cc 10 a v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage -1 v cc x 0.3 v v ol output low voltage i ol = 3ma 0.4 v v oh output high voltage i oh = -1ma, v cc +3v v cc - 0.8 v v oh output high voltage i oh = -0.4ma, v cc +3v v cc - 0.4 v endurance and data retention parameter min units minimum endurance 100,000 data changes per bit per register data retention 100 years capacitance symbol test test conditions max units c in/out (notes 8, 10) input/output capacitance (si) v out = 0v 8 pf c out (note 10) output capacitance (so) v out = 0v 8 pf c in (note 10) input capacitance (a0, cs , wp , hold , and sck) v in = 0v 6 pf power-up timing symbol parameter min max units t r v cc (note 10) v cc power-up rate 0.2 50 v/ms t pur (notes 10, 11) power-up to initiation of read operation 1 ms t puw (note 11) power-up to initiation of write operation 50 ms notes: 10. limits established by characteri zation and are not production tested. 11. t pur and t puw are the delays required from the time the (last) power supply (v cc -) is stable until the specif ic instruction can be issued. 12. esd rating on r h , r l , r w pins is 1.5kv (hbm, 1.0a leakage maximu m), esd rating on all other pins is 2.0kv. 13. parts are 100% tested at +25c. over-temperature limi ts established by characterization and are not production tested. a.c. test conditions i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 x9110
12 fn8158.3 february 13, 2008 equivalent a.c. load circuit 5v 1462 100pf so pin r h 10pf c l c l r w r total c w 25pf 10pf r l spice macro model 2714 2.7v 1382 100pf so pin 1217 ac timing symbol parameter min max units f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 400 ns t wh ssi/spi clock high time 150 ns t wl ssi/spi clock low time 150 ns t lead lead time 150 ns t lag lag time 150 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 50 ns t fi si, sck, hold and cs input fall time 50 ns t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 50 ns t hh hold hold time 50 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 100 ns t wpasu wp , a0 setup time 0 ns t wpah wp , a0 hold time 0 ns x9110
13 fn8158.3 february 13, 2008 symbol table high-voltage write cycle timing symbol parameter typ max units t wr high-voltage write cycle time (store instructions) 5 10 ms xdcp timing symbol parameter min max units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instructions) 5 10 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x9110
14 fn8158.3 february 13, 2008 timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo x9110
15 fn8158.3 february 13, 2008 xdcp timing (for all load instructions) write protect and device address pins timing applications information basic configurations of electronic potentiometers ... cs sck si msb lsb r w t wrl ... so high impedance cs wp a0 a1 t wpasu t wpah (any instruction) v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current x9110
16 fn8158.3 february 13, 2008 application circuits noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k 10k 10k 10k -12v +12v tl072 + ? v s v o r 2 r 1 } } x9110
17 fn8158.3 february 13, 2008 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o x9110
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8158.3 february 13, 2008 x9110 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06

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